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TDA19978B
Quad HDMI 1.3a receiver interface with equalizer (HDTV up to 1080p, up to UXGA for PC formats)
Rev. 02 -- 10 May 2010 Product data sheet
1. General description
The TDA19978B is a four input HDMI 1.3a compliant receiver with embedded EDID memory. The built-in auto-adaptive equalizer improves signal quality and allows the use of cable lengths up to 25 m which are laboratory tested with a 0.5 mm (24 AWG) cable at 2.05 gigasamples per second. In addition, the TDA19978B is delivered with software drivers to ease configuration and use. The TDA19978B supports:
* TV resolutions:
- 480i (1440 x 480i at 60 Hz), 576i (1440 x 576i at 50 Hz) to HDTV (up to 1920 x 1080p at 50/60 Hz) - WUXGA (1920 x 1200p at 60 Hz) reduced blanking format
* PC resolutions:
- VGA (640 x 480p at 60 Hz) to UXGA (1600 x 1200p at 60 Hz)
* Deep Color mode in 10-bit and 12-bit (up to 205 MHz TMDS clock) * Gamut boundary description * IEC 60958/IEC 61937, OBA (One Bit Audio), DST (Direct Stream Transfer) and HBR
(High Bit Rate) stream The TDA19978B includes:
* An enhanced PC and TV format recognition system * Generation of a 128/256/512 x fs system clock allowing the use of simple audio DACs
without an integrated PLL (such as the UDA1334BTS)
* An embedded oscillator (an external crystal can also be used) * Improved audio clock generation using an external reference clock * OBA (as used in SACD), DST and HBR stream support
The TDA19978B converts HDMI streams without HDCP into RGB or YCbCr digital signals. The YCbCr digital output signal can be 4:4:4 or 4:2:2 semi-planar format based on the ITU-R BT.601 standard or 4:2:2 based on the ITU-R BT.656 format. The device can adjust the output timing of the video port by altering the values of tsu(Q) and th(Q). In addition, all settings are controllable using the I2C-bus.
NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
2. Features and benefits
Complies with the HDMI 1.3a, DVI 1.0 and CEA-861-D Four (quad) independent HDMI inputs, up to the HDMI frequency of 205 MHz Embedded auto-adaptive equalizer on all HDMI links EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input Supports color depth processing (8-bit, 10-bit or 12-bit per color) Color gamut metadata packet with interrupt on each update, readable via the I2C-bus Up to four S/PDIF or I2S-bus outputs (eight channels) at a sampling rate up to 192 kHz with IEC 60958/IEC 61937 stream HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I2S-bus outputs HBR streams (e.g. DTS-HD master audio and Dolby TrueHD up to eight channels due to HBR packet for stream with a frame rate up to 768 kHz) support DSD and DST audio stream up to six DSD channels output for SACD with DST audio packet support Channel status decoder supports multi-channel reception Improved audio clock generation using an external reference clock System/master clock output (128/256/512 x fs) enables the use of the UDA1334BTS The HDMI interface supports: All HDTV formats up to 1920 x 1080p at 50/60 Hz and WUXGA (1920 x 1200p at 60 Hz) with support for reduced blanking PC formats up to UXGA (1600 x 1200p at 60 Hz) Embedded oscillator (an external crystal can be used) Frame and field detection for interlaced video signal Sync timing measurements for format recognition Improved system for measurements of blanking and video active area allowing an accurate recognition of PC and TV formats Repeater capability Programmable color space input signal conversion from RGB-to-YCbCr or YCbCr-to-RGB Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656 8-bit, 10-bit or 12-bit output formats selectable using the I2C-bus (8-bit and 10-bit only in 4:4:4 format) I2C-bus adjustable timing of video port (tsu(Q) and th(Q)) Downsampling-by-two with selectable filters on Cb and Cr channels in 4:2:2 mode Internal video and audio pattern generator Controllable using the I2C-bus; 5 V tolerant and bit rate up to 400 kbit/s DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s LV-TTL outputs Power-down mode CMOS process 1.8 V and 3.3 V power supplies Lead-free (Pb) HLQFP144 package
TDA19978B_2
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
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NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
3. Applications
HDTV YCbCr or RGB high-speed video digitizer Projector, plasma and LCD TV Rear projection TV High-end TV Home theater amplifier DVD recorder AVR and HDMI splitter
4. Quick reference data
Table 1. Symbol fclk(max) fclk(max) Quick reference data Parameter RXxC-[1] 205 pin VCLK pin ACLK pin SYSCLK Supplies VDDH(3V3) HDMI supply voltage (3.3 V) VDDH(1V8) HDMI supply voltage (1.8 V) VDDI(3V3) input supply voltage (3.3 V) VDDC(1V8) core supply voltage (1.8 V) VDDO(3V3) output supply voltage (3.3 V) P power dissipation Active mode 720p at 60 Hz 1080p at 60 Hz 1080p at 60 Hz; Deep Color mode Pcons power consumption Power-down mode pin PD = HIGH I2C-bus; I2C-bus;
[1] [2] x = A, B, C or D. At 30 % activity on video port output.
[2]
Conditions
Min
Typ Max -
Unit MHz MHz MHz MHz
Digital inputs: pins RXxC+,
maximum clock frequency maximum clock frequency
Clock timing output: pins VCLK, ACLK and SYSCLK 165 25 50
3.135 3.3 1.71 1.71 1.8 1.8 3.135 3.3 3.135 3.3 -
3.465 V 1.89 1.89 V V 3.465 V 3.465 V W W W mW mW mW
0.75 1.13 1.63 1 4 150 -
EDID EDID; activity detection
5. Ordering information
Table 2. Ordering information Package Name TDA19978BHV HLQFP144 Description plastic thermal enhanced low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm; exposed die pad Version SOT612-3 Type number
TDA19978B_2
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(c) NXP B.V. 2010. All rights reserved.
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Product data sheet Rev. 02 -- 10 May 2010 4 of 38
TDA19978B_2
6. Block diagram
NXP Semiconductors
HDMI A (channels 0/1/2) HDMI A (channel A) RRX1 HDMI B (channels 0/1/2) HDMI B (channel B)
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TERMINATION RESISTANCE CONTROL
AP4/WS AUDIO PLL AUDIO FORMATTER AP0 to AP3 ACLK AP5/SYSCLK
TERMINATION RESISTANCE CONTROL TERMINATION RESISTANCE CONTROL EQUALIZER TERMINATION RESISTANCE CONTROL CRYSTAL OSCILLATOR SYNC TIMING MEASUREMENT I2C-BUS SLAVE INTERFACE
OTP MEMORY
PACKET EXTRACTION
AUDIO FIFO
HDMI C (channels 0/1/2) HDMI C (channel C) RRX2 HDMI D (channels 0/1/2) HDMI D (channel D) XTALIN/MCLK XTALOUT
DEREPEATER
UPSAMPLER
HDMI RECEIVER
COLOR DEPTH UNPACKING
VIDEO OUTPUT FORMATTER
VP[29:0]
VCLK
EDID MEMORY
POWER MANAGEMENT
Quad HDMI 1.3a receiver with digital processing
TDA19978B
VHREF TIMING GENERATOR
DE HS/HREF VS/VREF CS/FREF
SDA/SCL
HSDAA/ HSCLA
HSDAB/ HSCLB
HSDAC/ HSCLC
HSDAD/ HSCLD
TDA19978B
001aai415
Fig 1.
Block diagram of TDA19978B
NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
7. Pinning information
7.1 Pinning
144 109 108 73 72
001aai416
1
36
TDA19978BHV
37
Fig 2.
Pin configuration for TDA19978B
7.2 Pin description
Table 3. Symbol VSSC PD VDDH(3V3) RXDC+ RXDC- VSSH RXCC- RXCC+ VDDH(3V3) RXD0+ RXD0- VSSH RXC0- RXC0+ VDDH(1V8) RXD1+ RXD1- VSSH RXC1- RXC1+ VDDH(3V3) RXD2+ RXD2-
TDA19978B_2
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Type[1] Description G I P I I G I I P I I G I I P I I G I I P I I ground for the digital core power-down control input (active HIGH) HDMI receiver supply voltage; 3.3 V HDMI input D positive clock channel HDMI input D negative clock channel HDMI receiver ground HDMI input C negative clock channel HDMI input C positive clock channel HDMI receiver supply voltage; 3.3 V HDMI input D positive data channel 0 HDMI input D negative data channel 0 HDMI receiver ground HDMI input C negative data channel 0 HDMI input C positive data channel 0 HDMI receiver supply voltage; 1.8 V HDMI input D positive data channel 1 HDMI input D negative data channel 1 HDMI receiver ground HDMI input C negative data channel 1 HDMI input C positive data channel 1 HDMI receiver supply voltage; 3.3 V HDMI input D positive data channel 2 HDMI input D negative data channel 2
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TDA19978B
Quad HDMI 1.3a receiver with digital processing
Pin description ...continued Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Type[1] Description G I I P P P O G O O O O O G O O O P P G O O O O O O O O P O G O O O O O O O HDMI receiver ground HDMI input C negative data channel 2 HDMI input C positive data channel 2 OTP memory programming voltage[2] digital core supply voltage; 1.8 V video port output supply voltage; 3.3 V video clock output video port output ground composite synchronization output composite field output signal vertical synchronization output vertical reference output horizontal synchronization output horizontal reference output data enable output video port output bit 0 digital core ground video port output bit 1 video port output bit 2 video port output bit 3 video port output supply voltage; 3.3 V digital core supply voltage; 1.8 V video port output ground video port output bit 4 video port output bit 5 video port output bit 6 video port output bit 7 video port output bit 8 video port output bit 9 video port output bit 10 video port output bit 11 video port output supply voltage; 3.3 V video port output bit 12 video port output ground video port output bit 13 video port output bit 14 video port output bit 15 video port output bit 16 video port output bit 17 video port output bit 18 video port output bit 19
(c) NXP B.V. 2010. All rights reserved.
Table 3. Symbol VSSH RXC2- RXC2+ VPP VDDC(1V8) VDDO(3V3) VCLK VSSO CS/FREF VS/VREF HS/HREF DE VP[0] VSSC VP[1] VP[2] VP[3] VDDO(3V3) VDDC(1V8) VSSO VP[4] VP[5] VP[6] VP[7] VP[8] VP[9] VP[10] VP[11] VDDO(3V3) VP[12] VSSO VP[13] VP[14] VP[15] VP[16] VP[17] VP[18] VP[19]
TDA19978B_2
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Product data sheet
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NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
Pin description ...continued Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Type[1] Description O P P G O O O O O O O G P O O G O O O O O O P O G P P G P G P O I P O video port output bit 20 video port output supply voltage; 3.3 V digital core supply voltage; 1.8 V video port output ground video port output bit 21 video port output bit 22 video port output bit 23 video port output bit 24 video port output bit 25 video port output bit 26 video port output bit 27 digital core ground video port output supply voltage; 3.3 V video port output bit 28 video port output bit 29 video port output ground audio clock output audio port 0 output audio port 1 output audio port 2 output audio port 3 output audio port 4 output word select output video port output supply voltage; 3.3 V audio port 5 output system clock audio output video port output ground HDMI audio PLL supply voltage; 3.3 V HDMI audio PLL supply voltage; 3.3 V HDMI audio PLL ground HDMI audio PLL supply voltage; 1.8 V HDMI audio PLL ground digital core supply voltage; 1.8 V crystal oscillator output crystal oscillator input test pattern clock input digital inputs supply voltage; 3.3 V video activity indication output (open-drain); warns the external microprocessor that a special event has occurred; must be connected to a pull-up resistor; 5 V tolerant (active LOW) I2C-bus serial data input/output
(c) NXP B.V. 2010. All rights reserved.
Table 3. Symbol VP[20] VDDO(3V3) VDDC(1V8) VSSO VP[21] VP[22] VP[23] VP[24] VP[25] VP[26] VP[27] VSSC VDDO(3V3) VP[28] VP[29] VSSO ACLK AP0 AP1 AP2 AP3 AP4/WS VDDO(3V3)
AP5/SYSCLK VSSO VDDH(3V3) VDDH(3V3) VSSH VDDH(1V8) VSSH VDDC(1V8) XTALOUT XTALIN/MCLK VDDI(3V3) VAI
SDA
TDA19978B_2
97
I/O
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Product data sheet
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NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
Pin description ...continued Pin 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Type[1] Description I I/O I I/O I I P G I P P G I P I I G I I P I I G I I P I I G I I P I I G I I G P P I/O I2C-bus serial clock input HDMI input/output A DDC-bus serial data HDMI input A DDC-bus serial clock HDMI input/output B DDC-bus serial data HDMI input B DDC-bus serial clock reserved for test; connect to digital inputs ground (VSSC) HDMI deep PLL supply voltage; 3.3 V HDMI deep PLL ground HDMI inputs A and B termination resistance control digital core supply voltage; 1.8 V HDMI receiver supply voltage; 1.8 V digital core ground I2C-bus address control input HDMI receiver supply voltage; 3.3 V HDMI input B positive clock channel HDMI input B negative clock channel HDMI receiver ground HDMI input A negative clock channel HDMI input A positive clock channel HDMI receiver supply voltage; 3.3 V HDMI input B positive data channel 0 HDMI input B negative data channel 0 HDMI receiver ground HDMI input A negative data channel 0 HDMI input A positive data channel 0 HDMI receiver supply voltage; 1.8 V HDMI input B positive data channel 1 HDMI input B negative data channel 1 HDMI receiver ground HDMI input A negative data channel 1 HDMI input A positive data channel 1 HDMI receiver supply voltage; 3.3 V HDMI input B positive data channel 2 HDMI input B negative data channel 2 HDMI receiver ground HDMI input A negative data channel 2 HDMI input A positive data channel 2 HDMI receiver ground digital core supply voltage; 1.8 V digital core supply voltage; 1.8 V HDMI input/output C DDC-bus serial data
(c) NXP B.V. 2010. All rights reserved.
Table 3. Symbol SCL HSDAA HSCLA HSDAB HSCLB TEST0 VDDH(3V3) VSSH RRX1 VDDC(1V8) VDDH(1V8) VSSC A0 VDDH(3V3) RXBC+ RXBC- VSSH RXAC- RXAC+ VDDH(3V3) RXB0+ RXB0- VSSH RXA0- RXA0+ VDDH(1V8) RXB1+ RXB1- VSSH RXA1- RXA1+ VDDH(3V3) RXB2+ RXB2- VSSH RXA2- RXA2+ VSSH VDDC(1V8) VDDC(1V8) HSDAC
TDA19978B_2
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NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
Pin description ...continued Pin 139 140 141 142 143 144 Type[1] Description I I/O I P I P G HDMI input C DDC-bus serial clock HDMI input/output D DDC-bus serial data HDMI input D DDC-bus serial clock digital inputs supply voltage; 3.3 V HDMI inputs C and D termination resistance control HDMI receiver supply voltage; 1.8 V exposed die pad; connect to digital core ground (VSSC)
Table 3. Symbol HSCLC HSDAD HSCLD VDDI(3V3) RRX2 VDDH(1V8)
Exposed die pad
[1] [2]
P = power supply; G = ground; I = input; O = output and I/O = input/output. Connected to the ground of the HDMI receiver (VSSH) in normal operation.
8. Functional description
The TDA19978B converts digital data streams input by the HDMI sources into parallel digital data for use by media and video signal processing integrated circuits in devices for HDTV. Data streams can be decoded without HDCP protection. Outputs from the TDA19978B can be RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar format based on the ITU-R BT.601 standard or YCbCr 4:2:2 based on the ITU-R BT.656 format. Inputs can be both progressive and interlaced formats. The TDA19978B comprises a color space conversion block, downsampling filters and an embedded timing code function. In addition, the repeater function enables other HDMI devices to be connected to form an extended "total application".
8.1 Software drivers
Software drivers are provided for easy configuration and use of the TDA19978B. These drivers can be integrated with a large range of processors, with or without an operating system. They control activity detection, input selection, video mode identification, color conversion, Power-down modes and InfoFrame notification.
8.2 HDMI inputs
Control of the four HDMI inputs can be automatic using activity detection or using the I2C-bus. The HDMI receiver inputs are defined by pins RXx0+, RXx0-, RXx1+, RXx1-, RXx2+, RXx2-, RXxC+, RXxC-, RRX1, RRX2, HSCLx and HSDAx (x equals A, B, C or D as applicable).
8.3 Termination resistance control
The HDMI receiver input contains a termination resistance control set by an external resistor connected between pins RRXx and VDDH(3V3) (x equals 1 for inputs A and B or 2 for inputs C and D). Typically, the characteristic impedance is 50 and the default value of the external terminal control resistor is 12 k 1 %.
TDA19978B_2
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Product data sheet
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TDA19978B
Quad HDMI 1.3a receiver with digital processing
8.4 Equalizer
The auto-adaptive equalizer automatically measures and selects the settings which provide the best signal quality for each cable. This improves signal quality and enables the use of cable lengths up to 25 m (laboratory tested, contact NXP semiconductors for detailed information). The equalizer is fully automatic and consequently does not need any external control.
8.5 Activity detection
The TDA19978B uses activity detection to automatically select the active HDMI input. An internal, fully programmable, frequency filter controls activity detection. It sees only the activity on the HDMI inputs with a frequency range between the minimal frequency (22.5 MHz) and the maximal frequency (205 MHz). This activity detection can generate an interrupt enabling users to manage each HDMI input.
8.6 Color depth unpacking
In Deep Color mode, the TDA19978B receives several fragments of a pixel group at the HDMI link frequency. The color depth unpacking block translates the received pixel group into pixels at the pixel frequency. This operation is fully automatic and does not need any external control.
8.7 Derepeater
The HDMI source uses pixel repetition to increase the transmitted pixel clock frequency for transmitting video formats at native pixel rates below 25 Mpixel/s or to increase the number of audio sample packets in each line. The derepeater function discards repeated pixels and divides the clock to reproduce the native video format.
8.8 Upsample
The HDMI source can use YCbCr 4:2:2 pixel encoding which enables the number of bits allocated per component to be increased up to 12. The upsample function transforms this 12-bit YCbCr 4:2:2 data stream into a 12-bit YCbCr 4:4:4 data stream by repeating or linearly interpolating the chrominance pixels Cb and Cr. Upsampling mode is selected using the I2C-bus.
8.9 Packet extraction
Information sent during the Data Island periods is extracted from the HDMI data stream. Audio clock regeneration, general control and InfoFrames can be read using the I2C-bus while audio samples are sent to the audio FIFO. The TDA19978B can receive HDMI 1.3a packets, general control and color gamut metadata packets. In audio applications, the TDA19978B manages HBR packets for high bit rate compressed audio streams (IEC 61937), OBA samples and DST packets for one bit audio and SACD with DSD and DST audio streams.
TDA19978B_2
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Product data sheet
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NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
The TDA19978B includes a two-channel status decoder supporting multi-channel reception for audio sample packets. This enables the user to obtain channel status information from the IEC 60958/IEC 61937 stream such as:
* The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958) * Copyright protection * Sampling frequency
Refer to IEC 60958/IEC 61937 specifications for more details. An update of each InfoFrame or the channel status content is indicated by a register bit and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary.
8.10 Audio PLL
The TDA19978B generates a 128/256/512 x fs system clock enabling the use of simple audio DACs without an integrated PLL, such as the UDA1334BTS. The programming of the audio PLL can be either automatic, using the audio clock regeneration parameters found in the Data Islands or set manually using the I2C-bus. All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz, 96 kHz and 192 kHz are accepted by the device.
8.11 Audio formatter
Audio samples can be output in either S/PDIF, I2S-bus formats or DSD (SACD). In I2S-bus or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins (AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using these pins. The audio port mapping depends on the channel allocation (see Table 4, Table 5 and Table 6 for detailed information).
TDA19978B_2
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TDA19978B
Quad HDMI 1.3a receiver with digital processing
Table 4. Audio port configuration (Layout 0) All audio ports are LV-TTL compatible. Audio port AP5 AP4 AP3 AP2 AP1 AP0 ACLK Pin 85 83 82 81 80 79 78 SD SCK (I2S-bus clock) 64 x fs 32 x fs
[1] Can be activated with the I2C-bus (optional).
Layout 0 I2S-bus SYSCLK[1] WS (word select) S/PDIF SYSCLK[1] WS[1] OBA
DSD channel 1 S/PDIF master clock for 64 x fs S/PDIF[1] DSD channel 0 DSD clock 64 x fs
Table 5. Audio port configuration (Layout 1) All audio ports are LV-TTL compatible. Audio port AP5 AP4 AP3 AP2 AP1 AP0 ACLK Pin 85 83 82 81 80 79 78 Layout 1 I2S-bus SYSCLK[1] WS (word select) SD3 SD2 SD1 SD0 SCK (I2S-bus clock) 64 x fs 32 x fs
[1] Can be activated with the I2C-bus (optional).
S/PDIF SYSCLK[1] WS[1] S/PDIF3 S/PDIF2 S/PDIF1 S/PDIF0 master clock for 64 x fs S/PDIF[1]
OBA DSD channel 5 DSD channel 4 DSD channel 3 DSD channel 2 DSD channel 1 DSD channel 0 DSD clock 64 x fs
Table 6. Audio port configuration for HBR and DST packets All audio ports are LV-TTL compatible. Audio port AP5 AP4 AP3 AP2 AP1 AP0 ACLK Pin 85 83 82 81 80 79 78 HBR demultiplexed I2S-bus SYSCLK[1] WS (word select) SDx + 3 SDx + 2 SDx + 1 SDx SCK (I2S-bus clock) 64 x fs (ACR) 32 x fs (ACR)
[1]
TDA19978B_2
DST S/PDIF SYSCLK[1] WS[1] S/PDIFx + 3 S/PDIFx + 2 S/PDIFx + 1 S/PDIFx master clock for S/PDIF[1] 64 x fs DSD channel 0 DSD clock 64 x fs 128 x fs frame_start
Can be activated with the I2C-bus (optional).
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Product data sheet
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NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
8.12 Sync timing measurement
To assist input format recognition, the vertical/horizontal periods and the horizontal pulse width are measured based on the externally generated MCLK frequency (27 MHz crystal). This function has an accuracy of 1 LSB = 1 x MCLK period.
8.13 Format measurement timing
The TDA19978B includes an improved system for accurate recognition of PC and TV formats. This system measures the parameters of blanking and video active area. This function can be useful for example when the TDA19978B receives PC format data in HDMI or DVI modes.
8.14 Color space conversion
The color space conversion enables an RGB signal from the HDMI input to be converted into a YCbCr signal or converting the YCbCr signal from the HDMI input into an RGB signal. The color space conversion formula is: C 11 C 12 C 13 CY OO1 YG O11 = C 21 C 22 C 23 x RV + O12 + OO2 VR OO3 UB O13 C 31 C 32 C 33 BU
(1)
Activation of the color space conversion function and programming of all coefficients and offsets is done via the I2C-bus.
8.15 4:2:2 downsampling filters
These filters downsample the Cb and Cr signals by a factor of 2. A delay has been added to the G/Y channel corresponding to the downsample filters pipeline delay to make sure the Y channel is in phase with the Cb and Cr channels. Four different filters, from simple cut to ITU-R BT.601 compliant digital, can be selected using the I2C-bus.
8.16 Range control
The range control function truncates the range of data to remove super-white and super-black pixels at specified ceiling and floor values.
8.17 Dithering function
The error dispersal rounding (dithering) function can convert the color depth from 30-bit or 36-bit to reduced 30-bit or 24-bit color depth. When dithering is triggered, the TDA19978B applies round, truncate or noise-shaping algorithms. When the error dispersal rounding function is not used, the data coming from the filter is directly sent to the 4:2:2 formatter. The error dispersal rounding function works only with the active video signal.
TDA19978B_2
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Product data sheet
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TDA19978B
Quad HDMI 1.3a receiver with digital processing
8.18 4:2:2 formatter
The 4:2:2 formatter contains the YCbCr 4:2:2 semi-planar and the YCbCr 4:2:2 ITU-R BT.656 formatting functions. The selection of these functions is made using the I2C-bus.
* In YCbCr 4:2:2 mode: the data frequency of the Y signal is equal to the pixel clock
frequency. While the data frequency of the Cb and Cr signals is equal to half the pixel clock frequency
* In semi-planar mode: the output clock frequency should be the same as the pixel
clock frequency
* In ITU-R BT.656 mode: the data frequency should be the same as the formatter clock
frequency (e.g. pixel clock frequency x 2) The Start Active Video (SAV) and End Active Video (EAV) timing reference codes can be included in the data stream based on the HREF, VREF and FREF positions from the VHREF timing generator. Specific codes programmed using the I2C-bus can replace the data stream during the blanking period to mask gain and clamp calibration.
8.19 Video port selection
Each channel can be allocated to a specified video port using the I2C-bus (see Section 13 "Output video port formats (mapping examples)" on page 20) to optimize board layout at the interface with video processing ICs. For example:
* * * *
R, G or B in RGB 4:4:4 mode on pins VP[29:20] Y, Cb or Cr in YUV 4:4:4 mode on pins VP[19:10] Y or Cb-Cr in 4:2:2 semi-planar mode on pins VP[9:0] Cb-Y-Cr-Y in 4:2:2 ITU-R BT.656 mode on pins VP[9:0]
Each video port can be set to high-impedance using the I2C-bus.
8.20 Output buffers
The output buffers are LV-TTL compatible. The outputs can be switched between active and high-impedance by the I2C-bus. The outputs HREF, VREF and FREF can be set to high-impedance (Z) or forced LOW (L), independently of the timing reference codes.
8.21 VHREF timing generator
The VHREF timing generator outputs all of the timing signals used by the device:
* VREF, HREF and FREF signals for SAV, EAV and active video area definition * VS and HS to change width and position compared with the HDMI inputs 8.22 I2C-bus serial interface
The I2C-bus serial interface enables the internal registers of the device to be programmed. The slave address of the device is selected by pin A0.
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8.23 Power management
The TDA19978B can use one of three Power-down modes:
* level 0: full Power-down mode * level 1: internal EDID memory with I2C-bus serial interface active * level 2: internal EDID memory with I2C-bus serial interface and activity detection
enabled The user can activate each mode with pin PD or using I2C-bus registers:
* level 0: PD pin is HIGH * level 1: settings defined in the I2C-bus registers * level 2: settings defined in the I2C-bus registers 8.24 EDID memory management
The TDA19978B embedded EDID memory can be shared with all HDMI inputs. The embedded EDID memory shares 253 bytes with the four HDMI inputs. In addition, three bytes are dedicated to the physical address and checksum for each HDMI input (see Figure 3). This memory is accessible in parallel by all HDMI inputs. You can share the EDID memory over zero, one, two, three or four HDMI input(s) as shown in Figure 4. The content of embedded volatile EDID memory must be programmed using the I2C-bus for each power-on of TDA19978B. The embedded EDID memory remains accessible on each HDMI input when the TDA19978B uses a different low-power mode. The "physical address" of each HDMI input can be easily changed with the TDA19978B without corrupting the integrity of each DDC-bus.
8.24.1 EDID memory shared over all four HDMI inputs
EDID: 253 B
TDA19978B
3B 3B 3B 3B
I2C-bus
CPU
HDMI INPUT
HDMI INPUT
HDMI INPUT
HDMI INPUT
FLASH(1) EDID CONTENT
001aai417
(1) 253 bytes + 3 bytes input A + 3 bytes input B + 3 bytes input C + 3 bytes input D + 1 byte address pointer (subPhys@): this indicates the address in each block where the data for inputs A, B, C and D will be copied.
Fig 3.
An example of an application with EDID memory shared over all four HDMI inputs
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8.24.2 EDID memory shared over three HDMI inputs
EDID: 253 B
TDA19978B
3B EXTERNAL EDID: 256 B or 512 B DVI or HDMI INPUT HDMI INPUT HDMI INPUT HDMI INPUT 3B 3B
I2C-bus
CPU
FLASH(1) EDID CONTENT
001aai418
(1) 253 bytes + 3 bytes input B + 3 bytes input C + 3 bytes input D + 1 byte address pointer (subPhys@): this indicates the address in each block where the data for inputs B, C and D will be copied.
Fig 4.
An example of an application with EDID shared over three HDMI inputs
9. I2C-bus protocol
The TDA19978B is a slave I2C-bus device and the SCL pin is only an input pin. The timing and protocol for I2C-bus are standard. Bit A0 of the I2C-bus device address is externally selected by the A0 pin. The main device I2C-bus address is given in Table 7.
Table 7. A6 1 I2C-bus slave address A5 0 A4 0 A3 1 A2 1 A1 0 A0 A0 R/W 0/1
10. Limiting values
Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDx(3V3) VDDx(1V8) VDD IO Tstg Tamb Tj VESD Parameter supply voltage on all 3.3 V pins supply voltage on all 1.8 V pins supply voltage difference output current storage temperature ambient temperature junction temperature electrostatic discharge voltage HBM Conditions Min -0.5 -0.5 -0.5 -55 0 -2000 Max +4.6 +2.5 +0.5 35 +150 70 125 +2000 Unit V V V mA C C C V
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11. Thermal characteristics
Table 9. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter thermal resistance from junction to case Conditions Typ 22.8 11.1 Unit K/W K/W thermal resistance from junction to ambient in free air
12. Characteristics
Table 10. Characteristics Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C; unless otherwise specified. Symbol Supplies VDDH(3V3) VDDH(1V8) VDDI(3V3) VDDC(1V8) VDDO(3V3) IDDH(3V3) HDMI supply voltage (3.3 V) HDMI supply voltage (1.8 V) input supply voltage (3.3 V) core supply voltage (1.8 V) output supply voltage (3.3 V) HDMI supply current (3.3 V) 720p at 60 Hz 1080p at 60 Hz 1080p at 60 Hz; Deep Color mode IDDH(1V8) HDMI supply current (1.8 V) 720p at 60 Hz 1080p at 60 Hz 1080p at 60 Hz; Deep Color mode IDDI(3V3) input supply current (3.3 V) 720p at 60 Hz 1080p at 60 Hz 1080p at 60 Hz; Deep Color mode IDDO(3V3) output supply current (3.3 V) 720p at 60 Hz 1080p at 60 Hz 1080p at 60 Hz; Deep Color mode IDDC(1V8) core supply current (1.8 V) 720p at 60 Hz 1080p at 60 Hz 1080p at 60 Hz; Deep Color mode VDD(3V3-3V3) supply voltage difference between two 3.3 V supplies VDD(1V8-1V8) supply voltage difference between two 1.8 V supplies P power dissipation start-up and established conditions start-up and established conditions Active mode 720p at 60 Hz 1080p at 60 Hz 1080p at 60 Hz; Deep Color mode
[1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1]
Parameter
Conditions
Min
Typ
Max 3.465 1.89 3.465 1.89 3.465 +100 +100
Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mV mV
3.135 3.3 1.71 1.71 -100 -100 1.8 1.8 103 106 110 48 68 85 1 1 1 49 78 120 148 283 453 3.135 3.3 3.135 3.3
-
0.75 1.13 1.63
-
W W W
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Table 10. Characteristics ...continued Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C; unless otherwise specified. Symbol Pcons Parameter power consumption Conditions Power-down mode pin PD = HIGH I2C-bus; Clock timing output: pins VCLK, ACLK and SYSCLK fclk(max) maximum clock frequency pin VCLK pin ACLK pin SYSCLK clk clock duty cycle pin VCLK pin ACLK pin SYSCLK Timing output: pins VP[29:0]; fs = 165 MHz; CL = 10 pF; see Figure 5 tsu(Q) th(Q) td(pipe) data output set-up time data output hold time pipeline delay time clock intervals from inputs to outputs; all modes 0.40 0.80 80 x Tclk 1.50 2.00 ns ns 165 25 50 50 50 50 MHz MHz MHz % % % EDID I2C-bus; EDID; activity detection 1 4 150 mW mW mW Min Typ Max Unit
Timing output: pins AP[5:0] with respect to pin ACLK; fclk = 12.288 MHz; CL = 10 pF; see Figure 6 tsu(Q) th(Q) VOL VOH ILOZ data output set-up time data output hold time LOW-level output voltage HIGH-level output voltage IOL = 2 mA IOH = -2 mA
[2]
69 2 2.4 10 -100 -
0 0
0.4 100 -10 -
ns ns V V A A A A
LV-TTL digital outputs: pins VP[29:0], VCLK, AP[5:0], ACLK, DE, HS, VS, HREF, VREF, FREF; CL = 10 pF
OFF-state output leakage current high-impedance state; VO = 0 V VO = VDDO(3V3) x 13 VO = VDDO(3V3) x VO = VDDO(3V3)
2 3
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Table 10. Characteristics ...continued Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C; unless otherwise specified. Symbol VI(dif) VI(cm) fclk(max) VI(dif) VI(cm) I2C-bus: fSCL Cb Ci DDC fSCL Ci
[1] [2]
Parameter RXxC-[3] differential input voltage common-mode input voltage maximum clock frequency
Conditions RRRX1 = 12 k 1 %; RRRX2 = 12 k 1 %
Min 150
Typ -
Max 1200 3.475 1200 3.475 400 400 10 100 400 10
Unit mV V MHz mV V kHz pF pF kHz kHz pF
Digital inputs: pins RXxC+,
2.735 205 RXx2-[3] 150 RRRX1 = 12 k 1 %; RRRX2 = 12 k 1 % -
Digital inputs: pins RXx0+, RXx0-, RXx1+, RXx1-, RXx2+, differential input voltage common-mode input voltage pins SCL and SDA[4] SCL clock frequency capacitive load for each bus line capacitance for each I/O pin I2C-bus: pins HSCLx, HSDAx SCL clock frequency capacitance for each I/O pin
At 30 % activity on video port output.
[3][5]
2.735 Standard-mode Fast-mode -
In high-impedance state, the output buffer is set to repeater mode recopying the input logic state with a small current. The output current changes from most negative to the most positive value at the triggering level which is internally set to VDDO(3V3) / 2 (e.g. the value of a pull-up or pull-down resistor must be lower than 18 k to have a stable output value of VDDO(3V3) or 0 V). x = A, B, C or D. Fast-mode, 5 V tolerant. 5 V tolerant.
[3] [4] [5]
VCLK tsu(Q)
50 %
2.4 V VP[29:0] 0.4 V th(Q)
001aah368
Fig 5.
Output timing diagram pin VCLK and pins VP[29:0]
ACLK tsu(Q) 2.4 V AP[5:0] 0.4 V th(Q)
001aah369
50 %
Fig 6.
Output timing diagram pin ACLK and pins AP[5:0]
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13. Output video port formats (mapping examples)
The following tables show examples of possible output formats that are enabled by the video port swap function in the driver.
Table 11. Signal VP[29] VP[28] VP[27] VP[26] VP[25] VP[24] VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12] VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0]
[1]
Output in 12-bit video port format (mapping example 1) YCbCr 4:2:2 semi-planar[1] Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Cb[1] Cb[0] Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:2:2 ITU-R BT.656[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Cb[1] Cb[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Z/L Z/L Z/L Z/L Z/L Z/L
Z = high-impedance; L = LOW-level; depending on the driver configuration.
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Table 12. Signal VP[29] VP[28] VP[27] VP[26] VP[25] VP[24] VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12] VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0]
[1]
Output in 12-bit video port format (mapping example 2) YCbCr 4:2:2 semi-planar[1] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Cb[1] Cb[0] Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Z/L Z/L Z/L Z/L Z/L Z/L Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:2:2 ITU-R BT.656[1] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Cb[1] Cb[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
Z = high-impedance; L = LOW-level; depending on the driver configuration.
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Table 13. Signal VP[29] VP[28] VP[27] VP[26] VP[25] VP[24] VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12] VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0]
[1]
Output in 10-bit video port format (mapping example 1) RGB G[11] G[10] G[9] G[8] G[7] G[6] G[5] G[4] G[3] G[2] R[11] R[10] R[9] R[8] R[7] R[6] R[5] R[4] R[3] R[2] B[11] B[10] B[9] B[8] B[7] B[6] B[5] B[4] B[3] B[2] YCbCr 4:4:4 Y[11] Y[10] Y[9] Y[8] Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] YCbCr 4:2:2 semi-planar[1] Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:2:2 ITU-R BT.656[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
Z = high-impedance; L = LOW-level; depending on the driver configuration.
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Table 14. Signal VP[29] VP[28] VP[27] VP[26] VP[25] VP[24] VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12] VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0]
[1]
Output in 10-bit video port format (mapping example 2) RGB B[11] B[10] B[9] B[8] B[7] B[6] B[5] B[4] B[3] B[2] G[11] G[10] G[9] G[8] G[7] G[6] G[5] G[4] G[3] G[2] R[11] R[10] R[9] R[8] R[7] R[6] R[5] R[4] R[3] R[2] YCbCr 4:4:4 Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Y[11] Y[10] Y[9] Y[8] Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] YCbCr 4:2:2 semi-planar[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] YCbCr 4:2:2 ITU-R BT.656[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2]
Z = high-impedance; L = LOW-level; depending on the driver configuration.
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Table 15. Signal VP[29] VP[28] VP[27] VP[26] VP[25] VP[24] VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12] VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0]
[1]
Output in 8-bit video port format (mapping example 1) RGB G[11] G[10] G[9] G[8] G[7] G[6] G[5] G[4] R[11] R[10] R[9] R[8] R[7] R[6] R[5] R[4] B[11] B[10] B[9] B[8] B[7] B[6] B[5] B[4] Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:4:4[1] Y[11] Y[10] Y[9] Y[8] Y[7] Y[6] Y[5] Y[4] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:2:2 semi-planar[1] Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:2:2 ITU-R BT.656[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L
Z = high-impedance; L = LOW-level; depending on the driver configuration.
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Quad HDMI 1.3a receiver with digital processing
Table 16. Signal VP[29] VP[28] VP[27] VP[26] VP[25] VP[24] VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12] VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0]
[1]
Output in 8-bit video port format (mapping example 2) RGB[1] YCbCr 4:4:4[1] B[11] B[10] B[9] B[8] B[7] B[6] B[5] B[4] G[11] G[10] G[9] G[8] G[7] G[6] G[5] G[4] R[11] R[10] R[9] R[8] R[7] R[6] R[5] R[4] Z/L Z/L Z/L Z/L Z/L Z/L Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Y[11] Y[10] Y[9] Y[8] Y[7] Y[6] Y[5] Y[4] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:2:2 semi-planar[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Z/L Z/L Z/L Z/L Z/L Z/L YCbCr 4:2:2 ITU-R BT.656[1] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cb[11] Cb[10] Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] Cb[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y0[11] Y0[10] Y0[9] Y0[8] Y0[7] Y0[6] Y0[5] Y0[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Cr[11] Cr[10] Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y1[11] Y1[10] Y1[9] Y1[8] Y1[7] Y1[6] Y1[5] Y1[4] Z/L Z/L Z/L Z/L Z/L Z/L
Z = high-impedance; L = LOW-level; depending on the driver configuration.
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14. Example of supported video formats
Table 17. Standard 576i[2] 480i[4] 576p 480p 720p Example of supported video formats Format 1440 x 576i 50 Hz 1440 x 480i 59.94 Hz 1440 x 480i 60 Hz 720 x 576p 50 Hz 720 x 480p 59.94 Hz 720 x 480p 60 Hz 1280 x 720p 50 Hz 1280 x 720p 59.94 Hz 1280 x 720p 60 Hz 1080i 1920 x 1080i 50 Hz 1920 x 1080i 59.94 Hz 1920 x 1080i 60 Hz 1080p 1920 x 1080p 50 Hz[5] Hz[5] 1920 x 1080p 59.94 0.31M3 VGA 640 x 480p 60 Hz 640 x 480p 72 Hz 640 x 480p 75 Hz 640 x 480p 85 Hz 0.48M3 SVGA 800 x 600p 56 Hz 800 x 600p 60 Hz 800 x 600p 72 Hz 800 x 600p 75 Hz 800 x 600p 85 Hz 0.48M3-R 0.41M9 0.79M3 XGA 800 x 600p 120 Hz 848 x 480p 60 Hz 1024 x 768p 43 Hz 1024 x 768p 60 Hz 1024 x 768p 70 Hz 1024 x 768p 75 Hz 1024 x 768p 85 Hz 0.79M3-R XGA 1.00M3 0.98M9-R 0.98M9 1024 x 768p 120 Hz 1152 x 864p 75 Hz 1280 x 768p 60 Hz 1280 x 768p 120 Hz[5] 1280 x 768p 60 Hz 1280 x 768p 75 Hz 1280 x 768p 85 Hz
TDA19978B_2
Total pixels x total lines 1728 x 625 1716 x 525 1716 x 525 864 x 625 858 x 525 858 x 525 1980 x 750 1650 x 750 1650 x 750 2640 x 1125 2200 x 1125 2200 x 1125 2640 x 1125 2200 x 1125 2200 x 1125 800 x 525 832 x 520 840 x 500 832 x 509 1024 x 625 1056 x 628 1040 x 666 1056 x 625 1048 x 631 960 x 636 1088 x 517 1264 x 817 1344 x 806 1328 x 806 1312 x 800 1376 x 808 1184 x 813 1600 x 900 1440 x 790 1440 x 813 1664 x 798 1696 x 805 1712 x 809
Horizontal rate Pixel clock (kHz) rate (MHz)[1] 15.750 15.734 15.750 31.250 31.469 31.500 37.500 44.955 45.000 28.125 33.716 33.750 56.250 67.433 67.500 31.469 37.861 37.500 43.269 35.156 37.879 48.077 46.875 53.674 76.302 31.020 35.522 48.363 56.476 60.023 68.677 97.551 67.500 47.396 97.396 47.776 60.289 68.633 27.000[3] 27.000[3] 27.027[3] 27.000 27.000 27.027 74.250 74.176 74.250 74.250 74.176 74.250 148.500 148.352 148.500 25.175 31.500 31.500 36.000 36.000 40.000 50.000 49.500 56.250 73.250 33.750 44.900 65.000 75.000 78.750 94.500 115.500 108.000 68.250 140.250 79.500 102.250 117.500
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1920 x 1080p 60 Hz[5]
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Example of supported video formats ...continued Format 1280 x 800p 60 Hz 1280 x 800p 120 Hz[5] 1280 x 800p 60 Hz 1280 x 800p 75 Hz 1280 x 800p 85 Hz Total pixels x total lines 1440 x 823 1440 x 847 1680 x 831 1696 x 838 1712 x 843 1800 x 1000 1728 x 1011 1688 x 1066 1688 x 1066 1728 x 1072 1792 x 795 1520 x 813 1560 x 1080 1864 x 1089 1896 x 1099 1600 x 926 1904 x 934 1936 x 942 1952 x 948 2160 x 1250 1840 x 1080 2240 x 1089 2080 x 1235 Horizontal rate Pixel clock (kHz) rate (MHz)[1] 49.306 101.563 49.702 62.795 71.554 60.000 85.938 63.981 79.976 91.146 47.712 97.533 64.744 65.317 82.278 55.469 55.935 70.635 80.430 75.000 64.674 65.290 74.038 71.000 146.250 83.500 106.500 122.500 108.000 148.500 108.000 135.000 157.500 85.500 148.250 101.000 121.750 156.000 88.750 106.500 136.750 157.000 162.000 119.000 146.250 154.000
Table 17. Standard 1.02MA-R 1.02MA
1.23M3 1.31M4 SXGA
1280 x 960p 60 Hz 1280 x 960p 85 Hz[5] 1280 x 1024p 60 Hz 1280 x 1024p 75 Hz 1280 x 1024p 85 Hz[5]
1.04M9 1.04M9-R 1.47M3-R 1.47M3 1.29MA-R 1.29MA
1360 x 768p 60 Hz 1360 x 768p 120 Hz[5] 1400 x 1050p 60 Hz 1400 x 1050p 60 Hz 1400 x 1050p 75 Hz[5] 1440 x 900p 60 Hz 1440 x 900p 60 Hz 1440 x 900p 75 1440 x 900p 85 Hz[5] Hz[5]
1.92M3 UXGA 1.76MA-R 1.76MA 2.30MA-R[6]
[1]
1600 x 1200p 60 Hz[5] 1680 x 1050p 60 Hz 1680 x 1050p 60 1920 x 1200p 60 Hz[5] Hz[5]
Pixel clock rate corresponds to VCLK output for 4:4:4 format and 4:2:2 semi-planar; VCLK / 2 for 4:2:2 ITU-R BT.656 format. The pixel clock rate can be determined by: a) Total pixels x total lines x frame rate for the progressive format. b) Total pixels x total lines x frame rate / 2 for the interlaced format.
[2] [3] [4] [5] [6]
Also referred to as PAL (Phase Alternating Line). Pixel-doubling. Also referred to as NTSC (National Television Standards Committee). Only supports Deep Color mode 10-bit. Sometimes also referred to as WUXGA (Wide Ultra eXtended Graphics Array).
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15. Application information
DDC C and D HDMI inputs A and B
1.8 VHDMI RRX2 12 k 1% 3.3 VHDMI VDDI(3V3) 3.3 VDIG_I 142 HSCLD 141 HSDAD 140 HSCLC 139 HSDAC 138 VDDC(1V8) 1.8 VDIG 137 VDDC(1V8) 1.8 VDIG 136 VSSH 135 RXA2+ 134 RXA2- 133 VSSH 132 RXB2- 131 RXB2+ 130 VDDH(3V3) 3.3 VHDMI 129 RXA1+ 128 RXA1- 127 VSSH 126 RXB1- 125 RXB1+ 124 VDDH(1V8) 1.8 VHDMI 123 RXA0+ 122 RXA0- 121 VSSH 120 RXB0- 119 RXB0+ 118 VDDH(3V3) 3.3 VHDMI 117 RXAC+ 116 RXAC- 115 VSSH 114 RXBC- 113 RXBC+ 112 VDDH(3V3) 3.3 VHDMI 111 A0 110 VSSC GNDC 109 144 143
VDDH(1V8)
GNDC 3.3 VHDMI
VSSC PD VDDH(3V3) RXDC+ RXDC- VSSH RXCC- RXCC+ VDDH(3V3) RXD0+ RXD0- VSSH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
3.3 VHDMI
RXC0- RXC0+ 1.8 VHDMI VDDH(1V8) RXD1+ RXD1- VSSH RXC1- RXC1+ 3.3 VHDMI VDDH(3V3) RXD2+ RXD2- VSSH RXC2- RXC2+ VPP 1.8 VDIG 3.3 VDIG VDDC(1V8) VDDO(3V3) VCLK VSSO CS/FREF VS/VREF HS/HREF DE VP[0]
TDA19978BHV
GNDC
1.8 VHDMI VDDC(1V8) 1.8 VDIG RRX1 12 k 1% 3.3 VHDMI 106 VSSH 105 VDDH(3V3) 3.3 VHDMI 104 TEST0 0 103 GNDC HSCLB 102 HSDAB 101 HSCLA 100 HSDAA 99 SCL 98 SDA 97 VAI 96 VDDI(3V3) 3.3 VDIG_I 95 XTALIN/MCLK 94 XTALOUT 93 VDDC(1V8) 1.8 VDIG 92 VSSH 91 VDDH(1V8) 1.8 VHDMI 90 VSSH 89 VDDH(3V3) 3.3 VHDMI 88 VDDH(3V3) 3.3 VHDMI 87 VSSO 86 AP5/SYSCLK 85 VDDO(3V3) 3.3 VDIG 84 AP4/WS 83 AP3 82 AP2 81 AP1 80 AP0 79 ACLK 78 VSSO 77 VP[29] 76 VP[28] 75 VDDO(3V3) 3.3 VDIG 74 VSSC 73 GNDC 108 107
VDDH(1V8)
HDMI inputs C and D
50
51
53
55
56
57
58
59
60
61
62
66
67
68
69
70
71
38
39
40
44
45
46
47
48
37
41
42
43
49
52
54
63
64
VDDO(3V3)
VDDO(3V3)
VDDO(3V3)
VDDC(1V8)
VDDC(1V8)
VSSC
VP[10]
VP[11]
VP[12]
VP[13]
VP[14]
VP[15]
VP[16]
VP[17]
VP[18]
VP[19]
VP[20]
65
VP[21]
VP[22]
VP[23]
VP[24]
VP[25]
VP[26]
GNDC
3.3 VDIG
1.8 VDIG
3.3 VDIG
3.3 VDIG
1.8 VDIG
VP[27]
VP[1]
VP[2]
VP[3]
VP[4]
VP[5]
VP[6]
VP[7]
VP[8]
VSSO
VP[9]
VSSO
VSSO
72
control outputs and video port outputs
001aai419
Fig 7.
Application diagram of TDA19978B
TDA19978B_2
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Product data sheet
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audio port output
27 MHz
I2C-bus DDC A and B
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Quad HDMI 1.3a receiver with digital processing
16. Package outline
HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm; exposed die pad
SOT612-3
c
y exposed die pad X
Dh 108 109 73 72 ZE
A
e
Eh
E HE
A A2
A1
(A 3) Lp L detail X
wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.12 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 20.1 19.9 Dh 5.7 5.5 E(1) 20.1 19.9 Eh 5.7 5.5 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 1.4 1.1 1.4 1.1 7 o 0
o
22.15 22.15 21.85 21.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT612-3 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-07-12 04-07-05
Fig 8.
TDA19978B_2
Package outline SOT612-3 (HLQFP144)
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17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19
Table 18. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 19. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 9.
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Quad HDMI 1.3a receiver with digital processing
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 9.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Abbreviations
Table 20. Acronym ACR AVR AWG CMOS DAC DDC-bus DSD DST DTS-HD DVD DVI EDID HBM HBR HD HDCP HDMI HDTV L-PCM
TDA19978B_2
Abbreviations Description Audio Clock Regeneration Audio Video Receiver American Wire Gauge Complementary Metal Oxide Semiconductor Digital-to-Analog Converter Display Data Channel bus Direct Stream Digital Direct Stream Transfer Digital Theater Systems High-Definition Digital Versatile Disc Digital Video Interface Extended Display Identification Data Human Body Model High Bit Rate High-Definition High-bandwidth Digital Content Protection High-Definition Multimedia Interface High-Definition TeleVision Linear-Pulse Code Modulation
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Quad HDMI 1.3a receiver with digital processing
Abbreviations ...continued Description Least Significant Bit Low Voltage Transistor-Transistor Logic National Television Standards Committee One Bit Audio One Time Programmable Phase Alternating Line Phase-Locked Loop Red Green Blue Super Audio CD Super Video Graphics Array Super eXtended Graphics Array Sony/Philips Digital Interface Format Transition Minimized Differential Signaling Ultra eXtended Graphics Array Video Graphics Array Wide Ultra eXtended Graphics Array eXtended Graphics Array Y = Luminance, Cb = Chroma blue, Cr = Chroma red Y = Luminance, U and V are chrominance signals
Table 20. Acronym LSB LV-TTL NTSC OBA OTP PAL PLL RGB SACD SVGA SXGA S/PDIF TMDS UXGA VGA WUXGA XGA YCbCr YUV
19. Revision history
Table 21. Revision history Release date 20100510 Data sheet status Product data sheet Change notice Supersedes TDA19978B_1 Document ID TDA19978B_2 Modifications:
* * * * * * *
Section 1 "General description": replaced 2.25 gigasamples per second by 2.05 gigasamples per second Section 1 "General description": updated the Deep Color mode in 12-bit Section 2 "Features and benefits": replaced 225 MHz by 205 MHz Table 1 "Quick reference data": updated Section 8.5 "Activity detection": replaced 225 MHz by 205 MHz Table 10 "Characteristics": updated Table 17 "Example of supported video formats": updated Product data sheet -
TDA19978B_1
20080807
TDA19978B_2
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Quad HDMI 1.3a receiver with digital processing
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2010. All rights reserved.
20.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
TDA19978B_2
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 02 -- 10 May 2010
34 of 38
NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
20.4 Licenses
Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org.
20.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA19978B_2
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 10 May 2010
35 of 38
NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
22. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Audio port configuration (Layout 0) . . . . . . . . .12 Audio port configuration (Layout 1) . . . . . . . . .12 Audio port configuration for HBR and DST packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 I2C-bus slave address . . . . . . . . . . . . . . . . . . .16 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .16 Thermal characteristics . . . . . . . . . . . . . . . . . .17 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .17 Output in 12-bit video port format (mapping example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Output in 12-bit video port format (mapping example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Output in 10-bit video port format (mapping example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Output in 10-bit video port format (mapping example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Output in 8-bit video port format (mapping example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Output in 8-bit video port format (mapping example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Example of supported video formats . . . . . . . .26 SnPb eutectic process (from J-STD-020C) . . .31 Lead-free process (from J-STD-020C) . . . . . .31 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .32 Revision history . . . . . . . . . . . . . . . . . . . . . . . .33
TDA19978B_2
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 10 May 2010
36 of 38
NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
23. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Block diagram of TDA19978B . . . . . . . . . . . . . . . .4 Pin configuration for TDA19978B . . . . . . . . . . . . .5 An example of an application with EDID memory shared over all four HDMI inputs . . . . . . . . . . . . .15 An example of an application with EDID shared over three HDMI inputs . . . . . . . . . . . . . . . . . . . .16 Output timing diagram pin VCLK and pins VP[29:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Output timing diagram pin ACLK and pins AP[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Application diagram of TDA19978B. . . . . . . . . . .28 Package outline SOT612-3 (HLQFP144) . . . . . .29 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
TDA19978B_2
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 10 May 2010
37 of 38
NXP Semiconductors
TDA19978B
Quad HDMI 1.3a receiver with digital processing
24. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.24.1 8.24.2 9 10 11 12 13 14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 9 Software drivers . . . . . . . . . . . . . . . . . . . . . . . . 9 HDMI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Termination resistance control . . . . . . . . . . . . . 9 Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Activity detection. . . . . . . . . . . . . . . . . . . . . . . 10 Color depth unpacking . . . . . . . . . . . . . . . . . . 10 Derepeater . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Upsample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Packet extraction . . . . . . . . . . . . . . . . . . . . . . 10 Audio PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Audio formatter . . . . . . . . . . . . . . . . . . . . . . . . 11 Sync timing measurement . . . . . . . . . . . . . . . 13 Format measurement timing. . . . . . . . . . . . . . 13 Color space conversion . . . . . . . . . . . . . . . . . 13 4:2:2 downsampling filters . . . . . . . . . . . . . . . 13 Range control . . . . . . . . . . . . . . . . . . . . . . . . . 13 Dithering function . . . . . . . . . . . . . . . . . . . . . . 13 4:2:2 formatter . . . . . . . . . . . . . . . . . . . . . . . . 14 Video port selection . . . . . . . . . . . . . . . . . . . . 14 Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . 14 VHREF timing generator . . . . . . . . . . . . . . . . 14 I2C-bus serial interface . . . . . . . . . . . . . . . . . . 14 Power management . . . . . . . . . . . . . . . . . . . . 15 EDID memory management . . . . . . . . . . . . . . 15 EDID memory shared over all four HDMI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EDID memory shared over three HDMI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . 16 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal characteristics . . . . . . . . . . . . . . . . . 17 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output video port formats (mapping examples) . . . . . . . . . . . . . . . . . . . . 20 Example of supported video formats. . . . . . . 26 15 16 17 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 20.5 21 22 23 24 Application information . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 30 30 30 30 31 32 33 34 34 34 34 35 35 35 36 37 38
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 May 2010 Document identifier: TDA19978B_2

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